[BANANA] Berkeley Lab - Scientific Computing Seminar, December 14, 2006

[Parry Husbands]

Date: Thursday, December 14, 2006
Time: 1:30pm-3:00pm
Location: Building 50F-1647

Seminar Speaker: Andrew Mihal
                  UC Berkeley
                  http://www.eecs.berkeley.edu/~mihal

Title: Hardware and Software Co-design for Managing Massive Concurrency

Abstract:

The now-common phrase "the processor is the NAND gate of the future" begs  
the
questions: "What kind of processor?" and "How to program them?". For many  
the
presumption is that the natural building block is a common and successful
general-purpose RISC processor and that programming will be done in C.  
Numerous
programmable multiprocessor systems of this type have been built, but they  
are
notoriously hard to program.

Programming is difficult because of concurrency. Embedded systems  
applications
have multiple flavors of concurrency on several levels of granularity:  
datatype-level,
data-level, and process-level. C is not a good language for capturing this  
concurrency,
and RISC processors are suboptimal architectures for implementing this  
concurrency.
The Cairn project aims to solve these challenges. The key idea is to give  
designers
the right concurrency abstractions for the different parts of the design  
problem:
applications, architectures, and mappings between applications and  
architectures.

This seminar will show how to implement concurrent applications written  
using models
of computation on novel Sub-RISC multiprocessors. These  
application-specific machines
break traditional architectural design patterns in order to better support  
the
application's concurrency requirements at low cost and with high  
performance. A
gigabit-rate network security gateway application will be described,  
implemented
with 344-bit wide processors for packet header processing and 1-bit wide  
processors
for intrusion detection.

Sponsor of Seminar: John Shalf